This invention relates to first-in-first-out (FIFO) memory devices and more specifically to FIFO memories which facilitate data communication between a host CPU and a peripheral device.
It is known in the art to use FIFO memories to facilitate data communication between a host CPU and a peripheral device. For example, U.S. Pat. No. 4,145,755 issued to Suzuki et al. discusses a system in which a CPU loads a FIFO memory with data. After the FIFO memory is filled with data, the data in the FIFO memory is transferred to a peripheral device. The Suzuki FIFO memory device provides flag signals to the host CPU indicating when the FIFO memory is full or empty. The system discussed in the '755 patent is relatively simple and only allows for data to be transferred from the host CPU to the peripheral device.
A more complicated system is discussed in U.S. Pat. No. 4,138,732 also issued to Suzuki et al. Illustrated as prior art in FIG. 1 of the '732 patent is a system employing two FIFO memories, one which facilitates communication of data from a host CPU to a peripheral device and a second FIFO memory which facilitates communication of data from the peripheral device to the host CPU.
Another type of FIFO memory is illustrated in FIG. 2 of the '732 patent. The FIFO memory of FIG. 2 includes a RAM which is addressed by a first up-down counter during transfer of data between a host CPU and the RAM. The contents of the first up-down counter can be preset to any desired value by the host CPU. Similarly, the RAM is also addressed by a second up-down counter during transfer of data between a peripheral device and the RAM. The second up-down counter can be preset to any desired value by the peripheral device. The FIF0 memory can pass information from the host CPU to the peripheral device or from the peripheral device to the host CPU.